(preliminary) pll500-15/16 low phase noise vcxo (1mhz to 18mhz) 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 10/12/06 page 1 features ? vcxo with divider selection (divsel) input pin ? pll500-15: 8, 16 ? pll500-16: 2, 4 ? vcxo output for the 1mhz to 18mhz range ? 16mhz to 36mhz fundamental crystal input. ? low phase noise (-130 dbc @ 10khz offset using a 35.328mhz crystal). ? cmos output with oe tri-state control. ? integrated high linearity variable capacitors. ? 12ma drive capability at ttl output. ? 150 ppm pull range, max 5% linearity. ? low jitter (rms): 2.5ps period jitter. ? 2.5v to 3.3v operation. ? available in 8-pin soic, 6-pin sot23 green / rohs compliant packages, or die. description the pll500-15/16 is a low cost, high performance and low phase noise vcxo for the 1.0mhz to 18mhz range, providing less than -130dbc at 10khz offset when using a 35.328mhz crys tal. the very low jitter (2.5 ps rms period jitter) makes this chip ideal for applications requiring voltage controlled frequency sources. input crystal ca n range from 16mhz to 36mhz (fundamental resonant mode). pin configuration divider selection logic levels part # divsel state operation 1 (default) 16 pll500-15 0 8 1 (default) 4 pll500-16 0 2 block diagram vcon xin vcxo clk selectable divider varicap xout divsel pll500-15/16 1 2 3 45 6 7 8 xin vcon divsel^ gnd xout vdd clk oe^ p500-15/16 1 2 34 5 6 xout vdd clk xin gnd vcon soic-8 sot23-6* ^: denotes internal pull-up *: sot package offers single divider option only
(preliminary) pll500-15/16 low phase noise vcxo (1mhz to 18mhz) 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 10/12/06 page 2 die pad layout die specifications name value size 39 x 32 mil reverse side gnd pad dimensions 80 micron x 80 micron thickness 10 mil package pin and die pad assignment pin# die pad position name sop-8 sot23-6 x ( m) y ( m) type description xin 1 6 94.183 768.599 i crystal input pin. vcon 2 5 94.157 605.029 p frequency control voltage input pin. divsel 3 - 94.183 331.756 i divider selection input pin. default logic 1 for sot23 package. see divider selection logic levels table on page 1. gnd 4 4 94.193 140.379 p ground pin. clk 5 3 715.472 203.866 o output clock pin. vdd 6 2 715.307 455.726 p vdd power supply pin. oe 7 - 715.472 626.716 i output enable input pin. disables the output when low. internal pull-up enables output by default if pin is not connected to low. default ?enabled? (logic 1) for sot23 package. xout 8 1 476.906 888.881 i crystal output pin. 5 y x (0,0) (812,986) 39 mil 32 mil 8 6 2 3 4 7 die id: pll500-15: c500a a1111-12 pll500-16: c500a a1111-11 1 xin divsel^ clk gnd vcon xout oe^ vdd note: ^ denotes internal pull up
(preliminary) pll500-15/16 low phase noise vcxo (1mhz to 18mhz) 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 10/12/06 page 3 electrical specifications 1. absolute maximum ratings parameters symbol min. max. units supply voltage v dd 4.6 v input voltage, dc v i -0.5 v dd +0.5 v output voltage, dc v o -0.5 v dd +0.5 v storage temperature t s -65 150 c ambient operating temperature* t a -40 85 c junction temperature t j 125 c lead temperature (soldering, 10s) 260 c esd protection, human body model 2 kv exposure of the device under conditions beyond the limits specified by maximum ratings for extended periods may cause permanent damage to the device and affect product reliability. these conditions represent a stress rating only, and functional operations of the device at th ese or any other conditions above the operational limits noted in this specification is not implied. *operating temperature is guaranteed by design. parts are tested to commercial grade only. 2. ac electrical specifications parameters symbol conditions min. typ. max. units input crystal frequency 16 36 mhz 0.8v ~ 2.0v with 10 pf load 1.15 output clock rise/fall time 0.3v ~ 3.0v with 15 pf load 3.7 ns output clock duty cycle measured @ 1.4v 45 50 55 % 3. voltage control crystal oscillator parameters symbol conditions min. typ. max. units vcxo stabilization time * t vcxostb from power valid 10 ms vcxo tuning range xtal c 0 /c 1 < 250 0v vcon 3.3v 300 ppm clk output pullability vcon=1.65v, 1.65v 150 ppm vcxo tuning characteristic 100 ppm/v pull range linearity 5 % power supply rejection pwsrr frequency change with vdd varied +/- 10% -1 +1 ppm vcon pin input impedance 2000 k ? vcon modulation bw 0v vcon 3.3v, -3db 45 khz note: parameters denoted with an asterisk (*) represent nominal charac terization data and are not production tested to any specific limits.
(preliminary) pll500-15/16 low phase noise vcxo (1mhz to 18mhz) 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 10/12/06 page 4 4. jitter and phase noise specifications parameters conditions min. typ. max. units rms period jitter (1 sigma ? 1000 samples) with capacitive decoupling between vdd and gnd. 2.5 ps phase noise relative to carrier 18m hz @100hz offset -75 dbc/hz phase noise relative to carrier 18m hz @1khz offset -105 dbc/hz phase noise relative to carrier 18m hz @10khz offset -125 dbc/hz phase noise relative to carrier 18m hz @100khz offset -133 dbc/hz phase noise relative to carrier 18m hz @1mhz offset -140 dbc/hz 5. dc specifications parameters symbol conditions min. typ. max. units supply current, dynamic, with loaded outputs i dd f xin = 36mhz output load of 15pf 5 6 ma operating voltage v dd 2.25 3.63 v output low voltage at cmos level v olc i ol = +4ma 0.4 v output high voltage at cmos level v ohc i oh = -4ma v dd ? 0.4 v output drive current for v ol <0.4v or v oh >2.4v 8 9.5 ma vcxo control voltage vcon 0 v dd v 6. crystal specifications parameters symbol min. typ. max. units crystal resonator frequency f xin 16 36 mhz crystal loading rating (vcon = 1.65v) c l (xtal) 8.5 pf maximum sustainable drive level 200 w operating drive level 50 w c0 5 pf c0/c1 250 - esr r s 30 ? note : the crystal must be such that it oscillates (parallel re sonant) at nominal frequency when presented a c load as specified abo ve. if the crystal requires more load to be at nominal frequency, th e additional load must be added externally. this however may r educe the pull range.
(preliminary) pll500-15/16 low phase noise vcxo (1mhz to 18mhz) 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 10/12/06 page 5 package drawings ( green package co mpliant) soic 8l sot-23 6l dimension in mm symbol min. max. a 1.35 1.75 a1 0.10 0.25 a2 1.25 1.50 b 0.33 0.53 c 0.19 0.27 d 4.80 5.00 e 3.80 4.00 h 5.80 6.20 l 0.40 0.89 e 1.27 bsc dimension in mm symbol min. max. a 1.05 1.35 a1 0.05 0.15 a2 1.00 1.20 b 0.30 0.50 c 0.08 0.20 d 2.80 3.00 e 1.50 1.70 h 2.60 3.00 l 0.35 0.55 e 0.95 bsc c l a2 e h d a1 e b a c l a2 e h d a1 e b a
(preliminary) pll500-15/16 low phase noise vcxo (1mhz to 18mhz) 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 10/12/06 page 6 ordering information ( green package compliant) phaselink corporation, reserves the right to make changes in its products or specifications, or bo th at any time without notice . the information fur- nished by phaselink is believed to be accurate and reliable. ho wever, phaselink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. life support policy : phaselink?s products are not authorized for use as critical components in life support devices or systems without the ex- press written approval of the president of phaselink corporation. for part ordering, please contact our sales department: 47745 fremont blvd., fremont, ca 94538, usa tel: (510) 492-0990 fax: (510) 492-0991 part number the order number for this device is a combination of the following: part number, package type and operating temperature range pll500-xx x x x x part / order number marking package option pll500-15dc p500-15dc die (waffle pack) pll500-15sc p500-15sc 8-pin soic (tube) pll500-15sc-r p500-15sc 8-pin soic (tape and reel) pll500-15scl p500-15scl 8-pin soic green (tube) pll500-15scl-r p500-15scl 8-pin soic green (tape and reel) pll500-15tc p500-15tc 6-pin sot23 (tube) pll500-15tc-r p500-15tc 6-pin sot23 (tape and reel) pll500-15tcl p500-15tcl 6-pin sot23 green (tube) pll500-15tcl-r p500-15tcl 6-pin sot23 green (tape and reel) pll500-16dc p500-16dc die (waffle pack) pll500-16sc p500-16sc 8-pin soic (tube) pll500-16sc-r p500-16sc 8-pin soic (tape and reel) pll500-16scl p500-16scl 8-pin soic green (tube) pll500-16scl-r p500-16scl 8-pin soic green (tape and reel) pll500-16tc p500-16tc 6-pin sot23 (tube) pll500-16tc-r p500-16tc 6-pin sot23 (tape and reel) PLL500-16TCL p500-16tcl 6-pin sot23 green (tube) PLL500-16TCL-r p500-16tcl 6-pin sot23 green (tape and reel) part number temperature c=commercial i=industrial package type d=die s= soic-8l t= sot23-6l none=normal pack a ge l=green package none= tube r=tape and reel
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